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TC1322
12-Bit Digital-to-Analog Converter with Two-Wire Interface
Features
* * * * * 12-Bit Digital-to-Analog Converter 2.7-5.5V Single Supply Operation Simple SMBus/I2CTM Serial Interface Low Power: 350A Operation, 0.5A Shutdown 8-Pin SOIC and 8-Pin MSOP Packages
General Description
The TC1322 is a serially accessible 12-bit voltage output digital-to-analog converter (DAC). The DAC produces an output voltage that ranges from ground to an externally supplied reference voltage. It operates from a single power supply that can range from 2.7V to 5.5V, making it ideal for a wide range of applications. Built into the part is a Power-on Reset function that ensures that the device starts at a known condition. Communication with the TC1322 is accomplished via a simple 2-wire SMBus/I2C compatible serial port with the TC1322 acting as a slave only device. The host can enable the SHDN bit in the CONFIG register to activate the Low Power Standby mode.
Applications
* Programmable Voltage Sources * Digital Controlled Amplifiers/Attenuators * Process Monitoring and Control
Device Selection Table
Part Number Package Temperature Range -40C to +85C -40C to +85C
Package Type
8-Pin MSOP and 8-Pin SOIC (Narrow)
VREF 1 SDA 2 SCL 3 GND 4 8 VDD DAC-OUT NC VOUT 7 6 5
TC1322EOA 8-Pin SOIC (Narrow) TC1322EUA 8-Pin MSOP
TC1322
Typical Application
VIN (8) VDD
TC1322
- VREF (1) DAC VOUT (5) + VADJUST
Serial Port (3) SCLK
(2)
SDAT
Microcontroller
2002 Microchip Technology Inc.
DS21388B-page 1
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TC1322
Functional Block Diagram
VDD Configuration Register
TC1322
SDA SCL
Serial Port Interface
Control
DAC-OUT
Data Register
DAC
VOUT
VREF
GND
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DS21388B-page 2
2002 Microchip Technology Inc.
TC1322
1.0 ELECTRICAL CHARACTERISTICS
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings*
Supply Voltage (V DD) ............................................. +6V Voltage on any Pin .... (GND - 0.3V) to (VDD + 0.3V) Current on any Pin ............................................ 50mA Package Thermal Resistance (JA)............ 330C C/W Operating Temperature (TA)........................ See Below Storage Temperature (TSTG) .............. -65C to +150C
TC1322 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VDD = 2.7V to 5.5V, -40C TA +85C, VREF = 1.2V, CL = 80pF, unless otherwise noted. Symbol Power Supply VDD IDD IDD-STANDBY Supply Voltage Operating Current Standby Supply Current 2.7 -- -- -- 0.35 0.1 5.5 0.5 1 -- mA A VDD = 5.5V, VREF = 1.2V Serial Port Inactive (Note 1) VDD = 3.3V Serial Port Inactive (Note 1) Parameter Min Typ Max Unit Test Conditions
Static Performance - Analog Section Resolution INL FSE DNL VOS TCV OS PSRR VREF IREF VSW ROUT IOUT ISC Integral Non-Linearity at FS, TA = +25C Full Scale Error Differential Non-Linearity, TA = +25C Offset Error at VOUT Offset Error Tempco at VOUT Power Supply Rejection Ratio Voltage Reference Range Reference Input Leakage Current Voltage Swing Output Resistance @ VOUT Output Current (Source or Sink) Output Short-Circuit Current VDD = 5.5V Voltage Output Slew Rate Output Voltage Full Scale Settling Time Wake-up Time Digital Feed through and Crosstalk Serial Port Interface VIH VIL VOL CIN ILEAK Logic Input High Logic Input Low SDA Output Low Input Capacitance SDA, SCL I/O Leakage 2.4 -- -- -- -- -- -- -- -- -- 5 -- VDD 0.6 0.4 0.6 0.4 1.0 V -- V V pF A IOL = 3mA (Sinking Current) IOL = 6mA -- -- -- -- -- -- -- 0 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- 0.3 10 80 -- -- -- 5.0 2 30 20 0.8 10 20 5 10 16 3 +4 8 -- -- VDD - 1.2 1.0 VREF -- -- 50 50 -- -- -- -- Bits LSB %FS LSB mV v/C dB V A V mA mA mA V/s sec s nV-s SDA = VDD , SCL = 100kHz Source Sink VREF (VDD - 1.2V) ROUT () VDD at DC All Codes (Note 2) (Note 2) (Note 2)
Dynamic Performance SR tSETTLE tWU
Note 1: SDA and SCL must be connected to VDD or GND. 2: Measured at VOUT 50mV referred to GND to avoid output buffer clipping.
2002 Microchip Technology Inc.
DS21388B-page 3
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TC1322
TC1322 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VDD = 2.7V to 5.5V, -40C TA +85C, VREF = 1.2V, CL = 80pF, unless otherwise noted. Symbol Serial Port AC Timing fSMB tIDLE tH(START) tSU(START) SMBus Clock Frequency Bus Free Time Prior to New Transition START Condition Hold Time START Condition Setup Time 10 4.7 4.0 4.7 -- -- -- -- 100 -- -- -- kHz sec sec sec 90% SCL to 10% SDA (for Repeated START Condition) Parameter Min Typ Max Unit Test Conditions
tSU(STOP) tH-DATA tSU-DATA tLOW tHIGH tF tR tPOR
STOP Condition Setup Time Data In Hold Time Data In Setup Time Low Clock Period High Clock Period SMBus Fall Time SMBus Rise Time Power-on Reset Delay
4.0 100 100 4.7 4 -- -- --
-- -- -- -- -- -- -- 500
-- -- -- -- -- 300 1000 --
sec nsec nsec sec sec nsec nsec sec 10% to 10% 90% to 90% 90% to 10% 10% to 90% VDD VPOR (Rising Edge)
Note 1: SDA and SCL must be connected to VDD or GND. 2: Measured at VOUT 50mV referred to GND to avoid output buffer clipping.
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DS21388B-page 4
2002 Microchip Technology Inc.
TC1322
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number 1 2 3 4 5 6 7
PIN FUNCTION TABLE
Symbol VREF SDA SCL GND VOUT NC DAC-OUT Type Input Bi-Directional Input Power Output None Output Description Input. Voltage Reference Input can range from 0V to 1.2V below VDD. Bi-directional. Serial data is transferred on the SMBus in both directions using this pin. Input. SMBus serial clock. Clocks data into and out of the TC1322. Ground. Output. Buffered DAC output voltage. This voltage is a function of the reference voltage and the contents of the DATA register. No connection. Output. Unbuffered DAC output voltage. This voltage is a function of the reference voltage and the contents of the DATA register. This output is unbuffered and care must be taken that the pin is connected only to a high-impedance node. Input. Positive power supply input. See electrical specifications.
8
VDD
Power
2002 Microchip Technology Inc.
DS21388B-page 5
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TC1322
3.0 DETAILED DESCRIPTION
3.3 Standby Mode
The TC1322 is a monolithic 10-bit digital-to-analog converter that is designed to operate from a single supply that can range from 2.7V to 5.5V. The DAC consists of a data register (DATA), a configuration register (CONFIG), and a current output amplifier. The TC1322 uses an external reference, which also determines the maximum output voltage. The TC1322 uses a current steering DAC based on an array of matched current sources. This current, along with a precision resistor, converts the contents of the Data register and VREF into an output voltage, VOUT given by: VOUT = V REF (DATA/4096) The TC1322 allows the host to put it into a Low Power (IDD = 0.5A, typical) Standby mode. In this mode, the D/A conversion is halted. The SMBus port operates normally. Standby mode is enabled by setting the SHDN bit in the CONFIG register. The table below summarizes this operation.
TABLE 3-1:
STANDBY MODE OPERATION
Operating Mode Normal Standby
SHDN Bit 0 1
3.4
SMBus Slave Address
3.1
Reference Input
The reference pin, V REF, is a buffered high-impedance input and because of this, the load regulation of the reference source needs only to be able to tolerate leakage levels of current (less than 1A). VREF accepts a voltage range from 0 to (VDD - 1.2V). Input capacitance is typically 10pF.
The TC1322 is internally programmed to have a default SMBus address value of 1001 000b. Seven other addresses are available by custom order (contact factory). See Figure 3-1 for location of address bits in SMBus protocol.
3.2
Output Amplifier
The TC1322 DAC output is buffered with an internal unity gain rail-to-rail input/output amplifier with a typical slew rate of 0.8V/sec. Maximum full scale transition settling time is 10sec to within 1/2LSB when loaded with 1k in parallel with 100pF.
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DS21388B-page 6
2002 Microchip Technology Inc.
TC1322
FIGURE 3-1: SMBus PROTOCOLS
Write 1-Byte Format
S Address 7-Bits Slave Address R/W 0 ACK Command 8-Bits Command Byte: selects which register you are writing to. R/W 0 ACK Command 8-Bits Command Byte: selects which register you are writing to. ACK ACK Data 8-Bits Data Byte: data goes into the register set by the command byte. Data 8-Bits ACK Data 8-Bits ACK P ACK P
Write 2-Byte Format
S Address 7-Bits Slave Address
Data Byte: data goes into the register set by the command byte.
Read 1-Byte Format
S Address 7-Bits R/W ACK Command 0 8-Bits ACK S Address 7-Bits R/W ACK Data 1 8-Bits NACK P
Slave Address
Command Byte: selects Slave Address: repeated Data Byte: reads from which register you are due to change in data the register set by the reading from. flow direction. command byte. R/W ACK Data 1 8-Bits Data 8-Bits
Read 2-Byte Format
S Address 7-Bits R/W ACK Command 0 8-Bits ACK S Address 7-Bits ACK NACK P
Slave Address
Command Byte: selects which register you are reading from.
Slave Address: repeated Data Byte: reads from due to change in data the register set by the flow direction. command byte.
Receive 1-Byte Format
S Address 7-Bits R/W ACK 1 Data 8-Bits NACK P
S = START Condition Data Byte: reads data from P = STOP Condition the register commanded by Shaded = Slave Transmission the last read byte or write byte transmission.
Receive 1-Byte Format
S Address 7-Bits R/W ACK 1 Data 8-Bits ACK Data 8-Bits NACK P
Data Byte: reads data from S = START Condition the register commanded by P = STOP Condition Shaded = Slave Transmission the last read byte or write byte transmission.
2002 Microchip Technology Inc.
DS21388B-page 7
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TC1322
4.0 SERIAL PORT OPERATION
4.1 START Condition (START)
The Serial Clock input (SCL) and bi-directional data port (SDA) form a 2-wire bi-directional serial port for programming and interrogating the TC1322. The following conventions are used in this bus architecture: The TC1322 continuously monitors the SDA and SCL lines for a START condition (a HIGH to LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met.
TABLE 4-1:
TC1322 SERIAL BUS CONVENTIONS
Explanation
4.2
Address Byte
Term
Transmitter The device sending data to the bus. Receiver Master The device receiving data from the bus. The device which controls the bus: initiating transfers (START), generating the clock, and terminating transfers (STOP). The device addressed by the master. A unique condition signaling the beginning of a transfer indicated by SDA falling (High - Low) while SCL is high. A unique condition signaling the end of a transfer indicated by SDA rising (Low - High) while SCL is high. A Receiver Acknowledges the receipt of each byte with this unique condition. The Receiver drives SDA low during SCL high of the ACK clock pulse. The Master provides the clock pulse for the ACK cycle. Communication is not possible because the bus is in use. When the bus is IDLE, both SDA and SCL will remain high. The state of SDA must remain stable during the High period of SCL, in order for a data bit to be considered valid. SDA only changes state while SCL is low during normal data transfers. (See START and STOP conditions.)
Slave START
Immediately following the START condition, the host must transmit the address byte to the TC1322. The 7-bit SMBus address for the TC1322 is 1001000. The 7-bit address transmitted in the serial bit stream must match for the TC1322 to respond with an Acknowledge (indicating the TC1322 is on the bus and ready to accept data). The eighth bit in the Address Byte is a Read-Write bit. This bit is a 1 for a read operation or 0 for a write operation. During the first phase of any transfer, this bit will be set = 0 to indicate that the command byte is being written.
STOP
4.3
Acknowledge (ACK)
ACK
Acknowledge (ACK) provides a positive handshake between the host and the TC1322. The host releases SDA after transmitting eight bits, then generates a ninth clock cycle to allow the TC1322 to pull the SDA line LOW to acknowledge that it successfully received the previous eight bits of data or address.
Busy Not Busy Data Valid
4.4
Data Byte
After a successful ACK of the address byte, the host must transmit the data byte to be written or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data byte into the TC1322.
4.5
STOP Condition (STOP)
All transfers take place under control of a host, usually a CPU or microcontroller acting as the Master, which provides the clock signal for all transfers. The TC1322 always operates as a Slave. The serial protocol is illustrated in Figure 3-1. All data transfers have two phases; all bytes are transferred MSB first. Accesses are initiated by a START condition (START), followed by a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a STOP condition (STOP). A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH are reserved for START and STOP conditions).
Communications must be terminated by a STOP condition (a LOW to HIGH transition of SDA while SCL is HIGH). The STOP Condition must be communicated by the transmitter to the TC1322. Refer to Figure 4-1, Timing Diagrams for serial bus timing.
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DS21388B-page 8
2002 Microchip Technology Inc.
TC1322
FIGURE 4-1: TIMING DIAGRAMS
SMBus Write Timing Diagram
A ILOW B IHIGH C D E F G H I J K
SCL SDA
tSU(START) tH(START) A = START Condition B = MSB of Address Clocked into Slave C = LSB of Address Clocked into Slave D = R/W Bit Clocked into Slave
tSU-DATA E = Slave Pulls SDA Line Low F = Acknowledge Bit Clocked into Master G = MSB of Data Clocked into Master H = LSB of Data Clocked into Master I = Acknowledge Clock Pulse J = STOP Condition K = New START Condition
tSU(STOP)
tIDLE
SMBus Read Timing Diagram
A ILOW B IHIGH C D E F G H I J K L M
SCL SDA
tSU(START) tH(START) A = START Condition B = MSB of Address Clocked into Slave C = LSB of Address Clocked into Slave D = R/W Bit Clocked into Slave E = Slave Pulls SDA Line Low
tSU-DATA
tH-DATA J = Acknowledge Clocked into Master K = Acknowledge Clock Pulse L = STOP Condition, Data Executed by Slave M = New START Condition
tSU(STOP) tIDLE
F = Acknowledge Bit Clocked into Master G = MSB of Data Clocked into Slave H = LSB of Data Clocked into Slave I = Slave Pulls SDA Line Low
2002 Microchip Technology Inc.
DS21388B-page 9
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TC1322
4.6 Register Set and Programmer's Model
TC1322 COMMAND SET (SMBus READ_BYTE AND WRITE_BYTE)
Command Byte Description Command RWD RWCR Code 00h 01h Function Read/Write Data (DATA) Read/Write Configuration (CONFIG) D[3] X
TABLE 4-4:
DATA REGISTER (DATA), 12-BIT, READ/WRITE
TABLE 4-2:
Data Register (DATA) for 1st Byte D[11] MSB D[0] X D[9] X D[8] X D[7] X D[6] X D[5] X D[4] LSB
Data Register (DATA) for 2nd Byte D[2] X D[1] X D[0] LSB X X X X X X X X
The DAC output voltage is a function of reference voltage and the binary value of the contents of the register DATA. The transfer function is given by the expression:
TABLE 4-3:
CONFIGURATION REGISTER (CONFIG), 8-BIT, READ/WRITE
EQUATION 4-1:

Configuration Register (CONFIG) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] SHDN Type Operation Read/ 1 = Standby Write 0 = Normal N/A N/A
VOUT = VREF x DATA 4096
Reserved Bit D[0] D[7]-D[1] POR 0 0 Function Standby Switch Reserved; Always returns Zero when Read
4.7
Register Set Summary
The TC1322's register set is summarized in Table 4-5 below. All registers are 12-bits wide.
TABLE 4-5:
TC1322 REGISTER SET SUMMARY
POR State 000000000000b Read Write X X X X
Name Data
Description Data Register (2-Byte Format)
Config CONFIG Register 0000 0000b
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DS21388B-page 10
2002 Microchip Technology Inc.

TC1322
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available at this time.
5.2
Taping Forms
Component Taping Orientation for 8-Pin MSOP Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
8-Pin MSOP
12 mm
8 mm
2500
13 in
Component Taping Orientation for 8-Pin SOIC (Narrow) Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
8-Pin SOIC (N)
12 mm
8 mm
2500
13 in
2002 Microchip Technology Inc.
DS21388B-page 11
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TC1322
5.3 Package Dimensions
8-Pin MSOP
PIN 1
.122 (3.10) .114 (2.90)
.197 (5.00) .189 (4.80)
.026 (0.65) TYP.
.122 (3.10) .114 (2.90) .043 (1.10) MAX. .016 (0.40) .010 (0.25) .006 (0.15) .002 (0.05)
6 MAX. .028 (0.70) .016 (0.40)
.008 (0.20) .005 (0.13)
Dimensions: inches (mm)
8-Pin SOIC
PIN 1
.157 (3.99) .150 (3.81)
.244 (6.20) .228 (5.79)
.050 (1.27) TYP.
.197 (5.00) .189 (4.80) .069 (1.75) .053 (1.35) .020 (0.51) .010 (0.25) .013 (0.33) .004 (0.10) .010 (0.25) .007 (0.18) .050 (1.27) .016 (0.40) Dimensions: inches (mm)
8 MAX. .
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DS21388B-page 12
2002 Microchip Technology Inc.
TC1322
NOTES:
2002 Microchip Technology Inc.
DS21388B-page 13
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TC1322
SALES AND SUPPORT
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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DS21388B-page 14
2002 Microchip Technology Inc.
TC1322
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21388B-page 15
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WORLDWIDE SALES AND SERVICE
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03/01/02
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DS21388B-page 16
2002 Microchip Technology Inc.
*B88312SD*

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